SystemVerilog: signed' and unsigned' typecast

`timescale 1ns/10ps
`define TRUE 1

module tt;

parameter int p1 = signed'(2);
parameter int p2 = signed'(-2);
parameter int p3 = unsigned'(2);
parameter int p4 = unsigned'(-2);

initial begin

$display("p1 = %d", p1);
$display("p2 = %d", p2);
$display("p3 = %d", p3);
$display("p4 = %d", p4);

end

endmodule


Simulator:
============
p1 = 2
p2 = -2
p3 = 2
p4 = -2

p4 = unsigned'(-2) not 2 because p4 is signed

VHDL: different entities instantiated with the same instance name sample

library IEEE;
use IEEE.std_logic_1164.all;

entity fa is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fa;


library IEEE;
use IEEE.std_logic_1164.all;

entity fb is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fb;


library IEEE;
use IEEE.std_logic_1164.all;

entity fc is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fc;


library IEEE;
use IEEE.std_logic_1164.all;

entity adder is
port(a,b:in std_logic;
c:in std_logic;
sum:out std_logic;
v,cout:out std_logic);
end entity adder;

architecture gate of fc is
begin
sum <= a xor b xor c;
end architecture gate;


architecture gate of fb is
component fc
port(a,b,c:in std_logic;
sum:out std_logic);
end component fc;
begin
inst:fc port map(a,b,c,sum);
sum <= a xor b xor c;
end architecture gate;



architecture gate of fa is
component fb
port(a,b,c:in std_logic;
sum:out std_logic);
end component fb;
begin
inst:fb port map(a,b,c,sum);
sum <= a xor b xor c;
end architecture gate;



architecture circuit of adder is
component fa
port(a,b,c:in std_logic;
sum:out std_logic);
end component fa;

begin
inst:fa port map(a,b,c,sum);
end architecture circuit;

SystemVerilog LRM 23: Compiler directives

Demo macro new usages
2 instances are instantiated: _regDout, _regDout2


`define DFF(q,i,clock) \
myDFF \_reg``q (.o(q),.clkb(clock ),.d(i)); \
module myDFF (output o, input clkb, d);
bit o;
bit clkb;
bit d;
assign o = d;
endmodule

module top;
bit clk, Din, Dout, Dout2;
genvar i;
generate
`DFF(Dout,Din,clk)
`DFF(Dout2,Din,clk)
endgenerate
endmodule

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