SystemVerilog LRM 23: Compiler directives

Demo macro new usages
2 instances are instantiated: _regDout, _regDout2


`define DFF(q,i,clock) \
myDFF \_reg``q (.o(q),.clkb(clock ),.d(i)); \
module myDFF (output o, input clkb, d);
bit o;
bit clkb;
bit d;
assign o = d;
endmodule

module top;
bit clk, Din, Dout, Dout2;
genvar i;
generate
`DFF(Dout,Din,clk)
`DFF(Dout2,Din,clk)
endgenerate
endmodule