library IEEE;
use IEEE.std_logic_1164.all;
entity fa is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fa;
library IEEE;
use IEEE.std_logic_1164.all;
entity fb is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fb;
library IEEE;
use IEEE.std_logic_1164.all;
entity fc is
port(a,b,c: in std_logic;
sum: out std_logic);
end entity fc;
library IEEE;
use IEEE.std_logic_1164.all;
entity adder is
port(a,b:in std_logic;
c:in std_logic;
sum:out std_logic;
v,cout:out std_logic);
end entity adder;
architecture gate of fc is
begin
sum <= a xor b xor c;
end architecture gate;
architecture gate of fb is
component fc
port(a,b,c:in std_logic;
sum:out std_logic);
end component fc;
begin
inst:fc port map(a,b,c,sum);
sum <= a xor b xor c;
end architecture gate;
architecture gate of fa is
component fb
port(a,b,c:in std_logic;
sum:out std_logic);
end component fb;
begin
inst:fb port map(a,b,c,sum);
sum <= a xor b xor c;
end architecture gate;
architecture circuit of adder is
component fa
port(a,b,c:in std_logic;
sum:out std_logic);
end component fa;
begin
inst:fa port map(a,b,c,sum);
end architecture circuit;
