SystemVerilog: signed' and unsigned' typecast

`timescale 1ns/10ps
`define TRUE 1

module tt;

parameter int p1 = signed'(2);
parameter int p2 = signed'(-2);
parameter int p3 = unsigned'(2);
parameter int p4 = unsigned'(-2);

initial begin

$display("p1 = %d", p1);
$display("p2 = %d", p2);
$display("p3 = %d", p3);
$display("p4 = %d", p4);

end

endmodule


Simulator:
============
p1 = 2
p2 = -2
p3 = 2
p4 = -2

p4 = unsigned'(-2) not 2 because p4 is signed